The present disclosure relates generally to computer simulation of physical processes, and more specifically to modelling and simulating nanowires in an integrated circuit (IC) for use in integrated circuit design and design automation.
A computer simulation is a simulation, run on a single computer, or a network of computers, to reproduce behavior of a physical system. The simulation applies an abstract model to simulate the system. Computer simulations have become a useful part of mathematical modeling of many natural systems in physics (computational physics), electronics, chemistry, and engineering. Simulation of a system is represented as the computer execution of the system's model. Computer simulation may be used to explore and gain insights into new technology and to estimate the performance or other behaviors of complex systems.
A nanowire is a nanostructure, with the diameter of the order of a nanometer (10−9 meters). At these scales, quantum mechanical effects are important. Many different types of nanowires exist, including superconducting (e.g., YBCO), metallic (e.g., Ni, Pt, Au), semiconducting (e.g., silicon nanowires (SiNWs), InP, GaN) and insulating (e.g., SiO2, TiO2).
There are many applications where nanowires may become important in electronic, opto-electronic and nanoelectromechanical devices, as additives in advanced composites, for metallic interconnects in nanoscale quantum devices, as field-emitters and as leads for biomolecular nanosensors. Therefore, the computer modelling and simulation of nano-wires and their physical behavior has become increasingly important.
Metal wires have been used for IC interconnects since invention of IC in early 70's. For the first several decades, the wires were manufactured with aluminum, but since the late 90's copper wires have been replacing aluminum for most of the ICs. Initially, due to the larger design rules, the wires were several microns wide. Currently, at 14 nm FinFET ICs, the copper interconnect wires on lower interconnect layers are about 30 nm wide. At the upcoming 7 nm and 5 nm technology nodes, the wire width is expected to reduce down to 15 nm, where ˜4 nm are taken by the two barrier layers that encapsulate the copper, with just 11 nm left for the copper wire. At such wire widths, copper resistivity is expected to more than double w.r.t. bulk copper resistivity. Resistivity is sharply increasing with the wire width scaling due to the increased electron scattering at the copper interfaces and grain boundaries, and grain size is proportional to the wire width.
The increase in wire resistance leads to increased delay of signal propagation through the wire from one circuit block to the next. To mitigate it, circuit designers are using so-called via pillars which is a structure that contains several vias propagating a connection from transistors that are below metal 0 to the high metal layers, say metal 5 or metal 6. The wires at high metal layers are wider and therefore provide lower resistance and lower signal delay. However, wider wires mean that there are fewer such wires available to connect circuit elements to each other. Besides, the via pillars take considerable area and therefore increase the cost of IC manufacturing. An accurate model to quantify different interconnect routing options is necessary to optimize performance of each particular IC to achieve its spec requirements.